MOCVD‐Grown MoS <sub>2</sub> Wafers as a Transfer‐Free Platform for Top‐Gate Devices via Dry Interface Engineering

S Shuhong Li J Juiteng Chang (Department of Materials Engineering The University of Tokyo Bunkyo Tokyo Japan) K Keisuke Atsumi K Kosei Matsumoto (Department of Materials Engineering The University of Tokyo Bunkyo Tokyo Japan) I Itsuki Tanaka (Department of Materials Engineering The University of Tokyo Bunkyo Tokyo Japan) T Tomonori Nishimura K Kaito Kanahashi (Department of Materials Engineering, The University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656, Japan) T Takahiro Nagata (Research Center for Electronic and Optical Materials, National Institute for Materials Science (NIMS) 3 , 1-1 Namiki, Tsukuba, Ibaraki 305-0044,) J Jun Nara Y Yoshiki Sakuma E Emi Kano N Nobuyuki Ikarashi K Kosuke Nagashio (Department of Materials Engineering, The University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656, Japan)

Abstract

ABSTRACT We uncover the electronic origin of hidden interfacial doping in monolayer MoS 2 single‐crystal wafers grown on sapphire by metal–organic chemical vapor deposition (MOCVD) and establish a transfer‐free top‐gate device platform. Despite structural perfection, as‐fabricated devices exhibit degenerate electron doping and lack a clear off state. Hall measurements quantify an interfacial electron density of 2.7 × 10 12 cm −2 , evidencing substantial charge transfer across the nominal van der Waals interface. Interface‐sensitive spectroscopy, lateral force microscopy, and thermal desorption analysis reveal a buried sulfate‐derived layer accompanied by a water‐like interfacial structure that acts as an intrinsic electron donor. A purely dry H 2 /Ar annealing process selectively removes these species, suppressing charge transfer and restoring intrinsic FET characteristics without transfer or wet processing. Through this dry interface engineering approach, we demonstrate MOCVD‐grown single‐crystal MoS 2 wafers as a robust, transfer‐free platform for the reliable evaluation of intrinsic gate stacks and device performance.

Article Details

Volume / Issue Vol. 38, Issue 45
Published August 01, 2026
ISSN 0935-9648
Publisher Unknown Publisher

Journal Info

Advanced Materials

Unknown Publisher

ISSN: 0935-9648 Physical Sciences

Authors (13)

S

Shuhong Li

J

Juiteng Chang

Department of Materials Engineering The University of Tokyo Bunkyo Tokyo Japan

K

Keisuke Atsumi

K

Kosei Matsumoto

Department of Materials Engineering The University of Tokyo Bunkyo Tokyo Japan

I

Itsuki Tanaka

Department of Materials Engineering The University of Tokyo Bunkyo Tokyo Japan

T

Tomonori Nishimura

K

Kaito Kanahashi

Department of Materials Engineering, The University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656, Japan

T

Takahiro Nagata

Research Center for Electronic and Optical Materials, National Institute for Materials Science (NIMS) 3 , 1-1 Namiki, Tsukuba, Ibaraki 305-0044,

J

Jun Nara

Y

Yoshiki Sakuma

E

Emi Kano

N

Nobuyuki Ikarashi

K

Kosuke Nagashio

Department of Materials Engineering, The University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656, Japan