Ultralow Voltage Operation of p‐ and n‐FETs Enabled by Self‐Formed Gate Dielectric and Metal Contacts on 2D Tellurium

Abstract

Abstract The ongoing demand for more energy‐efficient, high‐performance electronics is driving the exploration of innovative materials and device architectures, where interfaces play a crucial role due to the continuous downscaling of device dimensions. Tellurium (Te), in its 2D form, offers significant potential due to its high carrier mobility and ambipolar characteristics, with the carrier type easily tunable via surface modulation. In this study, atomically controlled material transformations in 2D Te are leveraged to create intimate junctions, enabling near‐ideal field‐effect transistors (FETs) for both n‐type and p‐type operation. A NiTe x ‐Te contact provides highly transparent interfaces, resulting in low contact resistance, while the TiO x ‐Te gate dielectric forms an ultraclean interface with a capacitance equivalent to 0.88 nm equivalent oxide thickness (EOT), where the quantum capacitance of Te is observed. Subthreshold slopes (SS) approach the Boltzmann limit, with a record‐low SS of 3.5 mV dec −1 achieved at 10 K. Furthermore, 2D Te‐based complementary metal‐oxide‐semiconductor (CMOS) inverters are demonstrated operating at an ultralow voltage of 0.08 V with a voltage gain of 7.1 V/V. This work presents a promising approach to forming intimate dielectric/semiconductor and metal/semiconductor junctions for next‐generation low‐power electronic devices.